The device size is 4 × 4 μm2. Every cycle data was captured during measurement. The P/E voltages were +2/−2.2 V. Both HRS and LRS were read out at +0.1 V, and pulse width was 500 μs. The P/E cycles are not stable as we expected. Further study is selleckchem needed to obtain stable P/E cycles. Long read pulse endurance of >106 cycles is shown in Figure 6b. In this case, stress pulse width was 500 μs and read pulse width was 10 μs. Stable LRS

is obtained at a V read of 0.1 V. Due to the strong conducting filament formation, stable LRS is observed under random read pulse. For LRS only, it took a long measurement time of approximately 3 days. On the other hand, the data retention is quite good after programming the device. The HRS was read out at two different V read’s of IWP-2 +0.1 and +0.05 V. Stable HRS is observed up to 400,000 cycles, and the HRS is decreased with pulse numbers. This may be due to defects creation during continuous see more stress on the TaO x switching layer or the migration of oxygen ions

due to heating effects. Further study is needed to improve P/E endurance and instability of read pulse endurance of HRS after long cycles. However, a resistance ratio of >10 is obtained after 106 cycles. Our memory device also performs good data retention of >104 s as shown in Figure 7. The read voltage for both HRS and LRS was −0.2 V. An acceptable resistance ratio of >10 is observed after a retention time of Astemizole 104 s. This RRAM device is very useful for nanoscale non-volatile memory application. Figure 6 Endurance characteristics. (a) P/E

endurance of >103 cycles and (b) long read pulse endurance of >106 cycles of our novel W/TaO x /TiN memory device. The device size is 4 × 4 μm2. Figure 7 Data retention characteristics. Good data retention of >104 s of our W/TaO x /TiN memory device. An acceptable resistance ratio of >10 is obtained after 104 s. Conclusions One hundred consecutive switching cycles in the W/TaO x /TiN structures under self-compliance (<200 μA) and low-voltage operation of ±2.5 V are obtained. The thicknesses of TaO x and TiO x N y layers are 7 and 3 nm, respectively, which are observed by HRTEM. The RRAM device sizes are also confirmed by TEM. Our memory device shows good switching characteristics at low self-current compliance with tight distribution of HRS/LRS, excellent device-to-device uniformity, and program/erase endurance of >1,000 cycles. The smaller size devices show better switching characteristics and uniformity as compared to the larger size devices, owing to the thinner W electrode as well as higher series resistance. Interfacial oxygen-rich TaO x layer acts as a series resistance to control the resistive switching characteristics which may also cause the self-compliance resistive switching behavior and non-linear I-V curve at LRS. Switching mechanism is based on the formation and rupture of oxygen vacancy conducting path in the TaO x switching material.